1. Field of the Invention
The present disclosure relates to memory controllers, and more particularly, to memory controllers for system-on-chip (SOC) operation.
2. Description of Related Art
In general, a system-on-chip (SOC) may include a memory controller for accessing an external memory. For example, the external memories accessed by the SOC may include non-volatile memories such as ROMs and Flash memories, used primarily to store programs, and volatile memories such as SRAMs and SDRAMs, used for various applications. An example of a conventional SOC is disclosed in U.S. Pat. No. 6,526,462.
FIG. 1 is a block diagram showing a SOC 10 comprising a conventional memory controller 12 and an external memory 20. The SOC 10 comprises the memory controller 12, intellectual property (IP) blocks 13 and 14, a microprocessor 15, an internal memory 16, and a direct memory access unit (DMA) 17. The SOC 10 may further comprise additional IP blocks and others, which are omitted for the sake of simplification. The memory controller 12, the IP blocks 13 and 14, the microprocessor 15, the internal memory 16, and the DMA 17, which are connected to a system bus 11, are in communication with each other. In addition, in some cases, data stored in the external memory 20 needs to be error-corrected. An error correcting code (ECC) processor (not shown) of an optical disk system as known in the art is an example of an apparatus for error-correcting the data stored in the external memory and rewriting data. The ECC processor reads error correcting data out of the data stored in the external memory and performs an XOR operation on the read data and calculated error mask data, and rewrites the result of the XOR operation to the external memory. Similarly to the ECC processor, one of the IP blocks 13 and 14 in the SOC 10 reads data stored in the external memory 20, modifies the read data, and rewrites the modified data to the external memory 20.
As shown in FIG. 1, the aforementioned operations are performed by the IP block 13. The IP block 13 requests the memory controller 12 to read data of the external memory 20 via the system bus 11. Next, the IP block 13 receives data read from the external memory 20 via the system bus 11 from the memory controller 12, as shown in line A. The IP block 13 modifies the read data and transmits the modified data to the memory controller 12 via the system bus 11, as shown in line B. The memory controller 12 writes the modified data received from the IP block 13 via the system bus 11 to the external memory 20.
Here, in order to use the system bus 11, the IP block 13 must acquire a privilege for the system bus 11 from an arbiter (not shown). In addition, in order to read the data stored in the external memory 20, the IP block 13 must acquire the privilege for the system bus 11 from the arbiter, and transmit a read address signal to the memory controller 12, and transmit a control data signal to the memory controller 12. In addition, in order to write the modified data to the external memory 20, the IP block 13 must acquire the privilege for the system bus 11 from the arbiter, transmit a write address signal to the memory controller 12, and transmit the modified data signal to the memory controller 12.
As described above, during an operation of modifying the data signal stored in the external memory 20, the IP block 13 occupies the system bus 11 twice. Therefore, there is a problem in that the occupation time of the IP block 13 occupying the system bus 11 is long. As a result, until the data transmission between the IP block 13 and the memory controller 12 is completed, other devices in the SOC 10 cannot use the system bus 11, so that overall performance of the SOC 10 may decrease. In addition, during the operation of modifying the data signal stored in the external memory 20, the address signal transmission and the data signal transmission between the IP block 13 and the memory controller 12 are performed twice, such that efficiency may be reduced.